A memory device is usually controlled by a memory controller, which, by sending commands to the memory device, can control, for example, operations of the memory device, such as reading or writing of the memory device. The controller's commands and data may be sent to the memory device via a data bus including one or more input/output lines or communication paths connecting with an interface of the memory device. The interface may be configured for parallel or serial communications transmitted according to a particular protocol.
Examples of a “read” and “write” protocol that may be used for serial communications are shown in the timing diagrams of FIGS. 1A and 1B. As shown in FIG. 1A, a controller may output a chip select signal 102 as a chip select output (CS#), a clock signal 104 as a clock output (CLK), and an access control signal 106 as one or more data input/outputs (DQ[7:0]). In the examples shown, a “low” chip select signal 102 enables serial access to the memory device for a command cycle, which extends for a duration of a plurality of clock pulses of the clock signal 104. The access control signal 106 for a read command, shown in FIG. 1A, includes a plurality of command (CMD) bits 110, which may include, for example, a 2-byte command signaling the memory device to start a read operation. Following the command bits, the access control signal includes a plurality of address bits 120, which may include, for example, a 4-byte address indicating a read address of the memory device. Next, the example read protocol includes a dummy cycle 125, as part of the access control signal 106, which may extend for a plurality of clock pulses, such as the four clock pulses shown, to wait for the memory device to prepare the data for output. After the dummy cycle 125, the access control signal 106 includes a plurality of read data bits 130. In the example shown, the controller may strobe the CMD bits 110 and the address bits 120 at rising edges of the clock signal 104, whereas the memory device may strobe the read data bits 130 at falling edges of the clock signal 104. The chip select signal 102 is then driven “high” to end the read command cycle.
An exemplary access control signal 108 for a write command, as shown in FIG. 1B, includes a plurality of CMD bits 140 signaling the memory device to start a write operation. The CMD bits 140 are followed by a plurality of address bits 150 indicating a write address of the memory device. The access control signal 108 then includes a plurality of data bits 160 constituting data to be written to the memory device. After outputting the data bits 160 according to the write protocol, the controller then drives the chip select signal “high” triggering the embedded write operation at the memory device.
In the examples shown in FIGS. 1A and 1B, proper read/write operations depend, in part, on complete and accurate transmission of the access control signals 106/108 between the memory and controller. As memory density increases and throughput demands require ever higher operating frequencies, the potential for information transmitted in the access control signal to be incorrectly sent or received by the memory or the controller increases. For example, propagation delays and noise effects may distort the command, address and data bits transmitted over the data bus DQ[7:0] resulting in incorrect transfer of the access control signals between the memory device and controller. Thus, memory systems may benefit from a serial communication protocol including error detection capability.